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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-23004-1E
ASSP
CMOS
3 V Single Power Supply Audio Interface Unit (AIU)
MB86435
s DESCRIPTION
The FUJITSU MB86435 is an AIU (audio interface unit) LSI for +3 V single-power source digital telephone devices, manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards, and can handle input and output in A-Law, -Law and linear conversion modes. The MB86435 also contains the necessary DTMF, microphone and receiver amps for telephone devices.
s FEATURES
* +3 V single power supply * Low power consumption: muting settings for each operating mode Normal operation : 6.0 mA TYP (speaker amp mute) Tone generation : 1.8 mA TYP (speaker amp mute) Standby mode : 0.5 A TYP * On-chip codec filter meets G.712 standards * Selection of codec conversion methods (A-law, -law, linear) * On-chip low-noise microphone amp (2-channel) (0 to 35 dB amplification) * On-chip receiver speaker amps (32 BTL type: 6.4 mW MIN) * On-chip tone speaker amp (25 BTL type: 10 mW MIN) * On-chip earphone speaker amps (32 single type: 2 mW MIN)
(Continued)
s PACKAGE
64 pin, Plastic LQFP
(FPT-64P-M03)
MB86435
(Continued)
* * * * * On-chip electronic volume gain adjustments (sending, receiving, tone) On-chip accessory input/output circuits DTMF generator function Service tone generation CMOS compatible input/output
s PIN ASSIGNMENT
(TOP VIEW) 64 1 Index 49 48
16 17 (FPT-64P-M03) 32
33
2
MB86435
s PIN DESCRIPTION
Pin No. 1 2 3 6 Symbol VRH SGC VDDAC SYNC I/O O O P I A/D A A A D Description Bypass capacitor connector pin for the A/D D/A reference voltage generator circuit. Place capacitor between VRH and CAG pins. Bypass capacitor connector pin for the signal ground potential generator circuit. Place capacitor between SGC and CAG pins. Analog power supply pin for codec block. To be set within range 2.7 to 3.6 V. PCM codec send/receive synchronization signal input pin. Operating clock frequency 8 kHz. CMOS interface. Constant H/L level signal will cause part of codec block to power-down. Send/receive PCM signal series bit rate setting input pin. Data rate for -law, A-law modes may be set to any level in the range 64 k to 3.152 MHz, and for linear mode in the range 256 k to 3.152 MHz. Constant H or L level signal will cause part of codec block to power-down. CMOS interface. PCM signal input pin. This signal is picked up internally at the fall of the CLK signal. CMOS interface. PCM signal output pin. Data is output in sync with the rise of the CLK signal. After data output, loses PLL synchronization, and at power-down this signal is fixed at H level. CMOS interface. Digital power supply pin. To be set within range 2.7 to 3.6 V. Digital ground pin. To be set to 0V. Power-down control signal input pin. CMOS interface. Used with PSC1,2 pins for power-down settings. Power-down control signal input pin. CMOS interface. Used with PSC0,2 pins for power-down settings. Power-down control signal input pin. CMOS interface. Used with PSC0,1 pins for power-down settings.
7
CLK
I
D
8 9 10 11 12
DIN DOUT VDD DG PSC0
I O P G I
D D D D D
13
PSC1
I
D
PSC 2 1 0 0 0 0 Full power-down 1 0 0 VREF operating -- 1 0 Tone operating -- -- 1 All operations available (--: value not determined)
14 15 16 17 18 19 20
PSC2 SRD SRC STB XPRST LO0 LO1
I I I I I O O
D D D D D D D
9-bit serial data input pin. CMOS interface. Data is written at the rise of the signal from this pin. Clock input pin for 9-bit serial data writing. CMOS interface. Data is written at the rise of this pin. Serial data latch strobe signal. Data is latched by the L level signal. CMOS interface. Digital reset signal input pin. CMOS interface. L level: internal latch initialization H level: normal operation External control latch output pin. Outputs value D0 of address 1000. CMOS interface. External control latch output pin. Outputs value D1 of address 1000. CMOS interface.
(Continued)
3
MB86435
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Symbol LO2 LO3 TCLK TONC LED DSCK EXSD TAUD DSDT TONEO RAUD VDDSP1 JEAR XEAR EAR SPG1 SPG2 XTONE TONE IMTON VDDSP2 BBI IM3 BTO
I/O O O I I O I/O I/O I/O I O O P
A/D D D D D D A A A A A A A O
Description External control latch output pin. Outputs value D2 of address 1000. CMOS interface. External control latch output pin. Outputs value D3 of address 1000. CMOS interface. Tone generator clock input pin. Can be used as a tone CLK signal by using address 1110 D4D3 to subdivide the internal clock signal by factors of 1/1, 1/2, 1/4. CMOS interface. Tone generator cycle control input pin. CMOS interface. Hlevel signal outputs tone. Ring LED control output pin. CMOS interface. Can be connected to EXSD or TAUD by switching bus. Can be connected to DSCK or TAUD by switching bus. Can be connected to EXSD or DSCK by switching bus. Can be connected to RAUD by switching bus. Tone signal output pin. Output pin for external speaker, or audio test signal. Can be connected to DSDT by switching paths. Speaker amp power supply pin. To be set within range 2.7 to 3.6 V. Earphone speaker amp output pin. Capable of 2 mW output at 32 load. Receiver speaker amp output pin. Internally connected to EAR and BTL. Maximum output of 6.4 mW can be obtained at 32 load by connecting speaker between EAR and XEAR. Receiver speaker amp output pin. Connected to XEAR and BTL. Speaker amp ground pin. To be set to 0 V. Speaker amp ground pin. To be set to 0 V. Speaker amp tone output pin. Internally connected to TONE and BLT. Maximum output of 10 mW can be obtained at 25 load by connecting speaker between TONE and XTONE. Speaker amp tone output pin. When speaker amp is not used for tone, TONE should be shorted to IMTON. Speaker drive inverted (-) signal input pin. Can be used to adjust gain by connecting resistance to TONE and IMTON. Speaker amp power supply pin. To be set within range 2.7 to 3.6 V. AMP3 output pin. Should be included in HPF together with IM3, to prevent DC offset from entering speakers. AMP3 inverted (-) signal input pin. Receiving volume adjustment circuit output pin.
O O G G O O I P O I O
A A A A A A A A A A A
(Continued)
4
MB86435
(Continued)
Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 62 63 64 4, 5, 60, 61 Symbol OP2 IM2 OP1 IM1 PTBO BAG VDDAB XJMIC JMIC JMICO XMICI MIC MICO SGO BBO BTPI BTPO CAG NC I/O O I O I O G P I I O I I O O O I O G -- A/D A A A A A A A A A A A A A A A A A A -- Description AMP2 output pin. If AMP2 is not used, IM2 should be shorted to OP2. AMP2 inverted (-) signal input pin. Can form a circuit with OP2 to add sidetone or tone. Melody circuits, if used, can alsobe connected here. AMP1 output pin. Can form a circuit with IM1 to include LPF or HPF in receiving block. If AMP1 is not used, IM1 should be shorted to OP1. AMP1 inverted (-) signal input pin. PCM receiver output pin. Analog ground pin for sending, receiving blocks. To be set to 0 V. Analog power supply pin for sending, receiving blocks. To be set within range 2.7 to 3.6 V. Microphone amp (2) non-inverted (+) signal input pin. Microphone amp (2) inverted (-) signal input pin. Microphone amp (2) output pin. Microphone amp (1) non-inverted (+) signal input pin. Microphone amp (1) inverted (-) signal input pin. Microphone amp (1) output pin. Sending block signal ground potential output pin. Buffers SGC voltage. Sending analog signal output pin. PCM ENCODE block input OP amp negative input pin. PCM ENCODE block input OP amp output pin. Analog ground pin for codec block. To be set to 0 V. Not connected. To be left open.
5
MB86435
s BLOCK DIAGRAM
SGO(58) SGC(2) VRH(1) BTPO(63) BTPI(62) BBO(59)
+
VREF generator
+ SGC
0 dB (TYP) EV0 5bit
0 dB + SGC
SW3
+
VREF generator block DOUT (9) SYNC (6) CLK (7) DIN (8) PTBO (49) OP1 (47) IM1 (48) SGC OP2 (45) IM2 (46) SGC BTO (44) IM3 (43) BBI (42) TONEO (30) TCLK (23) SGC A/D PLL D/A 512K LPF 5bit BPF
Microphone amp (1)
MICO (57) MIC (56) XMIC (55) JMICO (54) JMIC (53) XJMIC (52) TAUD (28) EXSD (27) DSCK (26) DSDT (29)
Codec block 0 dB (TYP) -7.5 to 8dB EV1 0.5dB step
-7.5 to 8dB 0.5dB step Sending block
SW4
+ Microphone amp (2) SW5
SW10 SW11
+
AMP1
0 dB (TYP) -16 to 12dB EV2 4.0dB step 3bit Accessory block
SW12 0 dB SW8 SGC -10.32 dB + SW14 SW6 - PD +
+
RAUD (31)
AMP2
+
AMP3
PD 0 dB
EAR (35) -4.3 dB XEAR (34)
Receiving block SW2 1/N cycle 1/2 cycle TONC + 1/4 cycle 1/N cycle TONC TONE (2) generator TONE (1) generator 0 dB (TYP) EV3 -8.5dB Single-14 dBv dual -14 dBv -7.5 to 8dB 0.5dB step 5bit SW7
+
PD
SGC Receiver speaker drive block -2.5 dB +
PD
JEAR (33)
TONC (24) (51) VDDAB ( 3 ) VDDAC (32) VDDSP1 (41) VDDSP2 (10) VDD (36) SPG1 (37) SPG2 (64) CAG (50) BAG (11) DG
TONC
Earphone speaker drive block + SGC SW9 IMTON (40) TONE (39)
Tone generator block
PD 0 dB
DATA LATCH Control block
P SAVE
- PD + SGC Tone speaker drive block LED (25)
: V DD : GND
XTONE (38)
SRD SRC STB XPRST LO0 LO1 LO2 LO3 (15) (16) (17) (18) (19) (20) (21) (22)
: Digital input : Digital output : Analog input
PSC0 PSC1 PSC2 (12) (13) (14)
: Analog output
: Input/output
6
MB86435
s FUNCTIONAL DESCRIPTION
1. Register Settings The MB86435 IC chip controls all electronic volume, switching, tone generator circuits and power-down control circuits by means of the SRD, STB and SRC data input signals. The MB86435 uses a 9-bit serial data format consisting of a 4-bit address followed by 5 data bits. Data is picked up at the rise of the SRC signal, and latched by the STB L-level signal. The 9-bits of serial data preceding the STB signal are considered valid. These register settings are not reset at power-down. They can be reset when data is initialized by an XPRST L-level signal. (1) Mode Settings Control segment EV0 EV1 EV2 TX-MUTE 0 1 0 0 D4 * * * D0 RX-MUTE SW5 SW4 0 1 0 1 D4 * D2 D1 D0 SW3 SW8 SW6 SW9 0 1 1 0 D4 * D2 D1 D0 SW7 ATT Address Data bit Setting description Sending audio level adjustment. Adjusts EV0 gain. Sending audio level adjustment. Adjusts EV1 gain. Sending audio level adjustment. Adjusts EV2 gain. D0: Sending audio mute SW 3, 4, 5 on/off control. Mute: 1, Unmute: 0 D4: Sending audio mute SW 6, 7, 8, 9 on/ off control. Mute: 1, Unmute: 0 D0: TAUD mute SW 5 on/off control. Mute: 1, Unmute: 0 D1: JMIC mute SW 4 on/off control. Mute: 1, Unmute: 0 D2: MIC mute SW 3 on/off control. Mute: 1, Unmute: 0 D4: RAUD mute SW 8 on/off control. Mute: 1, Unmute: 0 D0: EAR, XEAR mute SW 6 on/off control. Mute: 1, Unmute: 0 D1: TONE, XTONE mute SW 9 on/off control. Mute: 1, Unmute: 0 D2: JEAR mute SW 7 on/off control. Mute: 1, Unmute: 0 D4: JEAR attenuation level switch. 0: -2.5 dB, 1: -8.5 dB.
Initial data bit setting (at reset) Remarks
A3 A2 A1 A0 D4 D3 D2 D1 D0 0 0 0 1 D4 D3 D2 D1 D0 0 0 1 0 D4 D3 D2 D1 D0 0011 * * D2 D1 D0
D4 D3 D2 D1 D0 01111 01111 * * 100 *2, *3 0* * *0 *3, *4 *2, *5 *1
0* 000
*2
*3, *4, *6
0* 000
*4
(Continued)
7
MB86435
(Continued)
Control segment SW10 Address Data bit Setting description
Initial data bit setting (at reset) Remarks
A3 A2 A1 A0 D4 D3 D2 D1 D0 D0: EXSD pin selection SW 10 on/off control. On: 1, Off: 0 D1: DSDT pin selection SW 12 on/off control. On: 1, Off: 0 0 1 1 1 D4 D3 D2 D1 D0 D2: DSCK pin selection SW 12 on/off On: 1, Off: 0 D3: TONEO mute SW 2 on/off control. Mute: 1, Unmute: 0 D4: TONE sending add SW 14 on/off control. On: 1, Off: 0 1000 * D3 D2 D1 D0 Parallel output D3 = LO3, D2 = LO2, D1 = LO1, D0 = LO0
D4 D3 D2 D1 D0 *3, *5
SW12 SW11 SW2 SW14 Serial/ parallel converter EV3
*3, *6 00000 *3, *5 *7
*0000 01111 00000 *0010 00000 *0010
*8 *1
Frequency control TONE control
Output control
Master clock control
PCM
1 0 0 1 D4 D3 D2 D1 D0 Tone level adjustment. Adjusts EV3 gain. 1 0 1 0 X8 X7 X6 X5 X4 Tone (1) frequency control, set by 8-bit value X7 to X0. X8 = 1 to output trapezoidal wave, X8 = 0 to 1 0 1 1 * X3 X2 X1 X0 output sine wave. 1 1 0 0 Y8 Y7 Y6 Y5 Y4 Tone (2) frequency control, set by 8-bit value Y7 to Y0. 1 1 0 1 * Y3 Y2 Y1 Y0 Y8 = 1 to output trapezoidal wave, Y8 = 0 to output sine wave. Tone generator control D0: tone (2) on/off control. On: 1, off: 0 D1: tone (1) on/off control. On: 1, off: 0 D2: LED output on/off control. On: 1, off: 0 Tone CLK 1 1 1 0 D4 D3 D2 D1 D0 D4, D3 0 0 : TCLK1/1 frequency selected 0 1 : TCLK1/2 frequency selected 1 0 : TCLK1/4 frequency selected 1 1 : Prohibited PCM control D1, D0 0 : -law mode selected 1 1 1 1 * * * D1 D0 0 1 0 : A-law mode selected 0 1 : linear mode selected 0 0 0 0 D4 D3 D2 D1 D0 Do not write in test mode.
*9, *10
*7, *11, *12
00111 *9
* * *00
*13, *14
TEST
00000
(Continued)
8
MB86435
*1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: *14: See (4) Electronic Volume Controls See (2) Sending Audio Mute Setting See 5. Power Saving Modes See (3) Receiving Audio Mute Settings See 2. Analog Input (2) Accessory Input See 3. Analog Output (2) Accessory Output See (5) Tone Generator Circuit * Tone Generator Control Output Level See (8) Parallel Output See (5) Tone Generator Circuit * Tone Frequency Control Registers See (5) Tone Generator Circuit * Tone Output Waveforms See (5) Tone Generator Circuit * Tone Output Controls See (5) Tone Generator Circuit * LED Output Controls See (6) Codec Input/Output See (7) The Codec SYNC Pin
9
MB86435
(2) Sending Audio Mute Settings Switches SW 3 to SW 5 have the following functions. Address 0100 signals have priority. Setting Address A3 0 -- -- Data bit -- -- -- -- -- : muted, A2 1 * * * * * * * * * * * * * * A1 0 * * * * * * * A0 0 1 0 0 0 0 0 0 A3 0 -- -- -- -- -- -- -- A2 1 * * * * * * * A1 0 A0 0 SW3 -- -- -- -- -- -- -- -- -- SW4 -- -- -- SW5 Switching setting
D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 ------ ---- -- 1 -- 0 1 1 -- 0 --
---- 0
----
----
: unmuted, -- : not determined
(3) Receiving Audio Mute Settings Switches SW 6 to SW 9 have the following functions. Address 0100 signals have priority. Setting Address A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 0 1 0 0 0 1 0 1 0 1 1 0 SW8 SW7 SW9 SW6 Switching setting
D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 1* 0* 0* Data bit 0* 0* 0* 0* 0* 0* : muted, * * * * * * * * * *-- *-- *-- *-- *-- *-- *-- *-- *-- -- * ------ -- * ------ -- * ------ -- * ------ 1 * ------ -- * ------ -- * ------ -- * ------ 0 * ------ -- * ------ -- * ---- 1 --* --1-- --* 1 ---- -- * ------ -- * ---- 0 --* --0 -- --* 0 ---- -- * ------
-- -- --
-- --
-- -- -- -- --
-- -- -- -- -- -- --
-- --
-- -- -- -- --
: unmuted, -- : not determined
10
MB86435
(4) Electronic Volume Controls There are four different electronic volume controls, EV0 through EV3, with the following specifications. Electronic volume control settings are made by the SRD, SRC and STB signals, and setting values are reset by the XPRST signal. However, settings are not reset by PSC0, PSC1, PSC2 power-down mode operations. Table 1 Data bit value D4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Relation of Volume Control Data bit Values to Gain EV0 sending gain adjustment Typ. -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 EV1 sending gain adjustment Typ. -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 EV2 sending gain adjustment Typ. -16 -12 -8 -4 0 4 8 12 EV3 sending gain adjustment Typ. -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
Step
Unit
dB
Note: Each setting value is determined in relation to the initial setting value. Returns to initial value at reset ( parts) EV2 data bits D4, D3 are *. Table 2 Volume control No. EV0 EV1 EV3 EV2 Condition Gain deviation, with respect to reference value shown in Table1 Input frequency = 1020 Hz Input level = - 20 dBv Volume Gain Deviation Min. Reference value - 0.5 dB Reference value - 1.0 dB Typ. Reference value Reference value Max. Reference value + 0.5 dB Reference value + 1.0 dB Unit
dB
11
MB86435
(5) Tone Generator Circuit * Tone Frequency Control Registers The tone generator uses a clock signal obtained by subdividing the TCLK clock signal input by 1/1, 1/2 or 1/4 according to the data bit in address 1110. Table 3 Address 1110 D4 0 0 1 1 D3 0 1 0 1 Tone Clock Frequency Register Control Tone generator clock signal (fIN) TCLK input clock signal TCLK input clock signal subdivided by 1/2 TCLK input clock signal subdivided by 1/4 Prohibited
Frequency settings available through the tone frequency control register are determined by the following formula. Frequency setting f = fIN/(12*(1+n)), n=1, 2, 3, ..., 255. (where fIN: tone generator clock signal frequency). Therefore the available frequency setting range when fIN = 512 kHz is between fmin = 167 Hz and fmax = 21333 Hz. Frequency settings corresponding to each DTMF rated reference frequency are shown in the following table.
Table 4 Rated reference frequency (generator frequency) 262 Hz 384 Hz Service tone (single tone) 400 Hz 2000 Hz 2600 Hz 697 Hz Low tone D T M F High tone 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz
Tone Frequency Register Control (Condition: 512 kHz) Address 1010/1100 Data bit D4 D3 D2 D1 D0 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 Address 1011/1101 Data bit D4 D3 D2 D1 D0 * * * * * * * * * * * * * 0 1 1 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 n Error
Tone type
Frequency setting 261.7 Hz 384.4 Hz 398.7 Hz 2031.7 Hz 2666.7 Hz 699.4 Hz 775.7 Hz 853.3 Hz 948.1 Hz 1219.0 Hz 1333.3 Hz 1471.3 Hz 1641.0 Hz
162 110 106 20 15 60 54 49 44 34 31 28 25
-0.11% 0.10% -0.32% 1.56% 2.50% 0.34% 0.74% 0.15% 0.75% 0.82% -0.20% -0.38% 0.48%
Note: * Setting values are BIN display values * Error represents frequency setting error with respect to rated reference frequency.
12
MB86435
* Tone Output Waveform The D4 data bit at address 1010, 1100 may be used to select either sine-wave or trapezoidal waveforms for tone output.
VH D 4=0 Sine wave output VL
1 VH D 4=1
Trapezoidal wave
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
output
VL
* Tone Output Control Tone output may be controlled by address and through the external tone control input pin TONC. In addition, the tone control offers a choice of sine or trapezoidal waveforms.
Address 1110 ~ ~ ~
DATA - - - D1 (Tone (1) control) Address 1110 DATA - - - - D0 (Tone (2) control)
~ ~ ~
~
TONC
~
~
TONEO
SGC
Single tone
* LED Output Controls Output from the LED output pins can be controlled by the TONC signal and the address 1110 data bit D2. When the TONC signal is H-level, and the address 1110 data bit D2 value is L-level, the output level will be high. Output levels are CMOS levels.
Address 1110 DATA - - D 2 - TONC ~ LED ~ ~~ ~
~ Dual tone
~
Single tone
: Disable
~ ~
~ ~ : Disable ~
13
MB86435
* Tone Generator Control Output Level (Condition: EV3 = 0 dB) External pins Tone generator Address Address circuit 1110 0111 operating data bits data bits mode Tone (1) Tone (2) Output pin mode LED L L SGC SGC -- -- SGC SGC SGC SGC SGC -- -- SGC -- -- -- -- L L L TONEO H-Z H-Z SGC H-Z -- -- SGC -14 dBv Single tone output -14 dBv Single tone output -14 dBv Dual tone output
Remarks
PSC2 PSC1 PSC0 TONC D2 D1 D0 D3 (SW2) 0 1 -- -- -- -- -- -- -- -- 0 0 1 or 1 1 or 1 1 or 1 1 or 1 1 or 1 1 or 1 1 or 1 1 or 1 0 0 -- -- 0 0 1 1 1 1 1 1 ------ ------ ------ ------ 1 ---- 0 ---- --1 --1 --0 --0 1 0 1 0 -- -- 0 1 -- -- 0 0 0 0
: Operational,
: Power down, H-Z : High-impedance, L: L-level fixed, SGC: SGC fixed
Note: When the TONC pin signal is L-level, the tone generator circuit counters will be reset. When a dual tone is generated at the time of reset, the initial phase settings for tone (1) and tone (2) will be in phase. * Example: When Tone (1), Tone (2) are at the same frequency:
TONE
H L
Tone (1) SGC
Tone (2) SGC
TONEO
SGC
14
MB86435
(6) Codec Input/Output Both the -law and A-law coding/decoding conversion processes used by the MB86435 codec are compatible with CCITT Recommendation G.711. In addition, linear coding in the form of 14-bit two's complement code can be output starting with MSB values.
SYNC Din, Dout MSB 12 11 10 1 LSB
MSB
Code
LSB 1111111 0000001 0000000 1111111 0000001
PTBO reference voltage (V) 0.7354 to 1.4991 1.5000 1.5009 to 2.2647
011111111 to 000000000 000000000 111111111 to 100000000
(7) The Codec SYNC Pin The codec block requires the input of an 8 kHz sampling clock signal at the SYNC pin, as well as a data transfer clock at the CLK pin. In order to conserve power consumption, whenever the SYNC pin or CLK pin signal is inactive, the system goes into SYNC power-down mode and stops code conversion. Also, if either the SYNC or CLK pins encounters jitter of 5 s or greater, the system may go into power-down mode.Table 1.10 shows the status of output pins in SYNC power-down mode. Pin symbol SGC SGO VRH DOUT PTBO BTPO Operation Normal operation (1.5 V) Normal operation (1.5 V) Normal operation (2.5 V) H-level fixed SGC High impedance
15
MB86435
(8) Parallel Output The LO0 to 3 pins carry latched output for external controls. The data written to address 1000 can be output through these pins. Output is CMOS output.
D3 Address 1000
D2
D1
D0
LO0 LO1 LO2 LO3 (Inside IC)
2. Analog Input Analog input signals in the MB86435 include the two microphone inputs and the three accessory input. (1) Microphone Amps The microphone amps take the incoming signal from the microphones and amplify it to any desired level of gain. The microphone lines are low-noise types for use with piezoelectric-ceramic or capacitor microphones, and are capable of a wide range of amplification. All microphones and amps must be coupled with capacitors to prevent amplification of offset signals.
Piezoelectric-ceramic type MICO
+
MIC XMIC
Mic
(Inside IC)
SGC
AG
Capacitor type MICO
+
V DD
MIC XMIC
Mic
(Inside IC)
SGC
AG
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MB86435
Table 5 Parameter Gain measurement range Minimum load level Maximum output level (2) Accessory Input Direct input from the TAUD to the codec unit is possible through SW5, without passing through the microphone amp. Care must be taken with the input signal in this case, however, because input resistance is not at highimpedance level. Microphone amp output may be added to the signal by using switching controls. In this case, the result will be at the additional output level. In addition, SW10 and SW11 may be used to transmit digital data from the TAUD to EXSD and DSCK, allowing the sending of fax or PC data without modification.
0dB SW5 TAUD CODEC
+
Microphone Amp Characteristics Characteristics (typ) 0 to 35 dB 50 k 0.75 VOP
SW10 EXSD SW11 SGC (Inside IC) DSCK
Note: TAUD, EXSD, and DSCK contain no digital buffers. If not used, TAUD, EXSD and DSCK should be connected to SGC.
3. Analog Output The MB86435 has a total of four analog output circuits, including the three speaker drive circuits (receiver, earphone and tone) and the accessory output. (1) Speaker Drive Amp The speaker drive amps include two circuits (receiver and tone) with BTL output and one system (earphone) with single output. Because the speaker amp requires relatively high levels of power, it is connected to speaker selection switches (sw6-sw9) for power-down mode selection. Two systems (receiver and earphone) have fixed gain levels, while the other system (tone) allows gain adjustment by means of external resistors. Table 6 Parameter Output type Load resistance *1 Load resistance *2 Load capacity *2 Final stage gain Maximum output power *1: *2: Speaker Drive Amp Output Standards Earphone speaker amp (JEAR) Single 32 (typ) 2.8 k (typ) 70 nF -2.5 dB/-8.5 dB (JEAR) 2 mW (min) Tone speaker amps (TONE, XTONE) BTL 25 (typ) 2.8 kW (typ) 70 nF -5 to 20 dB (between TONE-XTONE) 10 mW (min)
Receiver speaker amps (EAR, XEAR) BTL 32 (typ) 2.8 k (typ) 70 nF -4.3 dB (between EAR-XEAR) 6.4 mW (min)
Dynamic-type speaker Piezoelectric-ceramic type speaker 17
MB86435
* Analog Output Connection Example
EAR
+
SGC - 4.3 dB BBI SGC
+
R3 C3 R4
Receiver speaker Dynamic type: 32 (typ) Piezoelectric-ceramic type: 70 nF, 2.8 k (typ)
XEAR
-2.5dB
JEAR -8.5dB SGC
+
R3 C3
R5
Earphone speaker Dynamic type: 32 (typ) Piezoelectric-ceramic type: 70 nF, 2.8 k (typ)
IMTON R2 TONE
R1 BBI
+
SGC GdB 0dB
R3 C3 R4 XTONE (Inside IC) R3 C3
Tone speaker Dynamic type: 32 (typ) Piezoelectric-ceramic type: 70 nF, 2.8 kW (typ) G=20 LOG (2*R 2/R ) [dB]
+
SGC
Note: * R3, C3 should be given the respective values 80, 0.01 F in order to prevent unwanted oscillation. * If a piezoelectric-ceramic type microphone is used, R4, R5 should be given the respective values 20, 10 in order to prevent unwanted oscillation.
* Tone Speaker Amp Not Used
IMTON
+ SGC
TONE
0dB + SGC (Inside IC) XTONE
Note: When no tone speaker amp is used, the amp input IMTON and output TONE should be shorted together.
18
MB86435
(2) Accessory Output The accessory output (RAUD pin) can carry either digital or analog output signals, and is controlled by address 0101 data bit D4 (SW 8), and address 0111 data bit D1 (SW 12). When both SW 8 and SW 12 are in off position, the accessory outputline is in H-Z (high impedance) state. Caution: never place both SW 8 and SW 12 in on position at the same time. This may cause the MB86435 to function improperly. * SW12 in On Position
DSDT Digital signal input SW 12 RAUD Digital signal output (digital signal not buffered) (Inside IC)
A4 0
Address A3 A2 1 1
A1 1
D4 --
D3 --
Data bit D2 D1 -- 1
D0 --
* SW8 in On Position
Analog input BBI SW 8
+
RAUD Analog output 5 k
(Inside IC)
Can be driven with load resistance of 5 k or greater
A4 0 0
Address A3 A2 1 1 0 0
A1 0 1
D4 0 0
D3 * *
Data bit D2 D1 * -- * --
D0 -- --
19
MB86435
4. Receiver Connections It is possible to add tones and adjust sidetones by using amp 1,2 and 3 and the electronic volume control. When using amp 3, however, it is necessary to include HPF to avoid interference from the speaker amp DC. * Tone and Sidetone Addition by Inclusion of Secondary LPF and Primary HPF.
R1 IM1 C1 R2 C2 SGC AMP1 SGC OP1 R3 R4 R5 C3 TONEO (tone) BBO (sidetone) IM2 R6 OP2 AMP2 SGC R7 C4 Signal addition R4=R5=R6=R7=100 k C3=C4=0.1F PTBO (receiving)
+
Secondary LPF A= -R2/R3 /Q=1/C2 x (1/R1+1/R2+1/R3) 2=1/(R1 R3 C1 C2)
+
EV2 BTO C5 R8 R9 C6 IMTON AMP3 SGC (Inside IC) The following settings are necessary to comply with CCITT Recommendation R8=R9=100 k C5=0.039F Primary HPF A= -R9/R8 fc=1/(2C5 R8) C6=0.1F
+
IM3 BBI
* Amp1, Amp2 not used
IM1
+ IM1 AMP2 SGC AMP1 SGC (Inside IC) OP1 EV2 BTO open OP2
+
(Inside IC)
Note: When amps are not used, the amp input and output should be shorted together.
20
MB86435
* Tone and Sidetone Addition by Inclusion of Third-Order HPF
C7 C8 R11 SGC AMP1 SGC OP1 C9 R12 R13 C10 TONEO(tone) BBO(sidetone) IM2 OP2 AMP2 SGC R14 R15 C11 Signal addition R12 = R13 = R14 = R15 = 100 k C10 = C11 = 0.1F PTBO (receiving) Secondary HPF A = -C8/C9 /Q = 1/(R10 C9 C7)x(C7+C8+C9) 2 = 1/(R10 R11 C9 C7 )
R10 IM1 +
+
EV2 BTO C16 R16 R17 C17 IMTON AMP3 SGC (Inside IC) Primary HPF A = -R9/R8 fc = 1/(2C16 R8) C17 = 0.1F
+
IM3 BBI
21
MB86435
5. Power Saving Modes (1) Mode Selection The MB86435 power saving modes can be controlled by using the external control signal lines (3 lines). It is also possible to apply power saving modes to the speaker amps with high power consumption levels by writing changes to register settings. Whenever the MB86435 changes directly from a power-down mode to normal operating mode, there is a possibility that speaker tones may be produced. The recommended sequence of coding changes to go into normal mode is (VREF mode) (Tone mode) (Normal mode). Power Saving Modes
AdExternal Adpins dress dress Address 0110
Output pin status
TONE XTONE MICO BBO JMICO VRH CODEC EAR XEAR DOUT RAUD JEAR SGC SGO OP2 BTO PTBO BTPO OP1 BBI
Operating circuit status
TONE generator VREF generator
Receiving
Mode
PS PSPS C2 C1 C0 D4 D0
D
D
D
D
SW8 SW7 SW9 SW6 SW6 SW7 SW9 SW8
Power supply current (mA) (typ)
Sending
SW6 SW7 SW9 SW8
All Power- 0 0 0 -- -- down VREF 1 0 0 -- -- --1 0 1 --1 0 0 Tone --100 --1 0 0 --100 ---- 1 0 ---- 1 0 Normal -- -- 1 0 ---- 1 0 ---- 1 0 1 1 1 1 1 0 0 0 0 0
-- -- -- 0 1 1 1 0 1 1 1 0
-- -- -- 1 0 1 1 1 0 1 1 0
-- -- -- 1 1 0 1 1 1 0 1 0
-- ZA H-Z ZB H-Z H H-Z ZC H-Z H-Z H-Z -- -- 1 1 1 0 1 1 1 0 0 ZA ZA H-Z ZA H-Z ZB H-Z H ZA H-Z ZB H-Z H ZA H-Z ZB ZA ZA H-Z ZA H-Z ZB ZB H-Z H-Z H-Z ZB H-Z H H-Z H ZB H-Z H H-Z ZB H-Z H ZC H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z H-Z
* *
Accessory
Receiving
Earphone
Tone
0.0005 0.41 1.8 2.4 4.4 6.6 6.6 6.0 8.0 10.2 10.2 18.2
Note: *
: Operational, x: Power-down, H-Z: High impedance, H: H-level fixed * : High impedance may not be applied, depending on status of SW6, SW7, SW8. ZA : EAR and XEAR are floating, however high resistance connection between EAR and XEAR. ZB : TONE and XTONE are floating, however, high resistance connection between TONE and XTONE, and between SGO and XTONE. ZC : Floating, however high resistance connection between OP2 and BTO. Codec in [Normal] mode operates with SYNC = 8 kHz, CLK = 2048 kHz. * When RAUD is operating, address 0111 data bit D1 value should be "0" (SW12 off). * In tone mode, address 0111 data bit D3 should be "0" (SW2 on), and address 0111 data bit D4 should be "0" (SW14 off). * When the SYNC and CLK pin signals are fixed at either L-level or H-level, part of the codec unit will go into power-down mode. At this time the PTBO signal will be SGC level, BTPO will be H-Z, and VRH output will be approximately 4.0 V.
22
MB86435
s TIMING CHART
* Codec-Related Signals
[1] [2] [3] [4] [5] [6] [7] [8]
CLK
f S *1
fC
SYNC
i
ii
iii
iv
v
vi
vii
viii
DOUT
1 DIN (1)
2
3
4
5
6
7
8
(2)
(3)
[Enlarged view] (1) [1] [2]
CLK
t XS t SX
SYNC
t WSH i ii
DOUT
t CO (2) [5] [6] t ZD
CLK
tF 5 tR t DR 6 t RD
DIN
(3)
[7]
[8] tWCH t WCL vii t CO viii t DZ
CLK
DOUT
t DF
*1 From first CLK Down to second CLK Down, SYNC = H.
23
MB86435
* Microcomputer Data-Related Signals
XPRST t WRE A3 SRD A2 A1 A0 D4 D3 D2 D1 D0
SRC f SCLK STB
LO 0 to 3 (1) [Enlarged view] (1) SRD SRC t WL t SCB STB t DS D1 t SSC t HSC D0 t HCB t WH
LO 0 to 3
t LD
24
MB86435
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Power supply voltage Analog input voltage Digital input voltage Storage temperature Symbol VS VAIN VDIN Vstg Rating Min. -0.3 -0.3 -0.3 -55 Max. 7.0 +VS + 0.3 +VS + 0.3 +125 Unit V V V C
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s RECOMMENDED OPERATING CONDITIONS
Parameter Operating temperature Power supply voltage Digital input voltage Analog output load resistance Analog output load capacity Analog output load resistance* Analog output load capacity*2 Analog output load resistance*1 Analog output load capacity*
2 1
Symbol Ta VS VL RLB CLB RLE CLE RLJ CLJ RLT CLT RLM CLM RLM CLM VAOUT VAIN
Pin name -- VDD, VDDAB, VDDAC, VDDSP1 , VDDSP2 All digital input pins BBO, PTBO, TONEO, BTO, BTPO Between EAR-XEAR
Value Min. -20 2.7 0.0 75 -- -- -- -- -- -- -- 50 -- 5 -- 0.45 1.2 Typ. +25 3.0 -- -- -- 32 -- 32 -- 25 -- -- -- -- -- -- -- Max. +80 3.6 VS -- 20 -- 70 -- 70 -- 70 -- 20 -- 20 VDD-0.45 1.8
Unit C V V k pF nF nF nF k pF k pF V V
JEAR
Analog output load resistance*1 Analog output load capacity*2 Analog output load resistance Analog output load capacity Analog output load resistance*3 Analog output load capacity*3 Analog output voltage Analog input voltage *1: *2: *3: Dynamic typ speakers Piezoelectric type speakers When SW8 = on, SW12 = off
Between TONE-XTONE MICO, JMICO, SGO, BBI, OP1, OP2 RAUD All analog output pins All analog input pins
25
MB86435
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics Parameter Power supply current at full power-down mode Power supply current with VREF operating Power supply current with TONE operating Power supply current for normal operation (only speaker ampmute) Receiver amps EAR, XEAR Speaker amp power supply voltage Symbol IVSST1 Pin Conditions PSC0 = 0 : PSC1 = 0 : PSC2 = 0, Ain = AG, Din = L PSC0 = 0 : PSC1 = 0 : PSC2 = 1, Ain = SGC, Din = L PSC0 = 0 : PSC1 = 1, Ain = SGC, Din = ICN SW6 = SW7 = SW8 = SW9 = off PSC0 = 1, Ain = SGC, Din = ICN SW6 = SW7 = SW9 = off All VDD pins lVSST5 PSC0 = 0, PSC1 = 1, Ain = SGC, Din = ICN, Power supply current differential when SW6 is on/off. PSC0 = 0, PSC1 = 1, Ain = SGC, Din = ICN, Power supply current differential when SW7 is on/off. PSC0 = 0, PSC1 = 1, Ain = SGC, Din = ICN, Power supply current differential when SW9 is on/off. -- All digital input pins Between MIC-XMIC, between JMIC-XJMIC -- -- -- -- Value Min. -- Typ. 0.5 Max. 50 Unit A A
IVSST2
--
410
800
lVSST3
--
1.8
3.0
mA
IVSST4
--
6.0
8.5
mA
--
4.8
7.0
mA
Earphone amp JEAR
lVSST6
--
2.6
4.0
mA
Tone amps TONE, XTONE
lVSST8
--
4.8
7.0
mA
Digital input voltage Digital input current
VIH VIL IIH IIL VFM
VSx0.7 0 -- -- -10
-- -- -- -- --
VS VSx0.3 10 10 10
V V A A mA
Input offset voltage
(Continued)
26
MB86435
(Continued)
Parameter Symbol VFR Pin RAUD Between EAR-XEAR Conditions BBI = SGC SW8 = on, SW6 = SW7 = SW9 = SW12 = off BBI = SGC SW6 = on, SW7 = SW8 = SW9 = SW12 = off Value Min. -15 Typ. -- Max. 15 Unit mV
VFE Output offset voltage
-20
--
20
mV
VFT VFP VOH VOL
IMTON = SGC Between SW9 = on, SW6 = SW7 TONE-XTONE = SW8 = SW12 = off PTBO Between MIC0-BBO Between JMIC0-BBO SGC SGO VRH All digital output pins All digital output pins Between DSTD-RAUD Between TAUD-EXSD Between TAUD-DSCK Din = ICN, EV2 = 0 dB EV0 = 0 dB -- -- -- IOH = - 0.5 mA IOL = 0.5 mA SW12 = on, SW8 = off SW10 = on, SW11 = off SW11 = on, SW10 = off
-20 -100 -100 1.40 1.40 -- VSx0.8 0.0 -- -- --
-- -- -- 1.50 1.50 2.5 -- -- -- -- --
20 100 100 1.60 1.60 -- VS VSx0.2 2 2 2
mV mV mV V V V V V k k k
SGC output voltage SGO output voltage VRH output voltage Digital output voltage Digital output voltage Resistance between pins TAUD and DSCK Resistance between pins TAUD and EXSD Resistance between pins DSTD and RAUD
VSGC VSGO lVRH VOH VOL RDR RTE RDE
Note: Measurement conditions: s Standard Test Circuit
27
MB86435
2. AC Characteristics (1) Codec-Related Signals Parameter Digital input rise time Digital input fall time Shift clock frequency Shift clock pulse width (H) Shift clock pulse width (L) Sync frequency Sync pulse width SYNC to CLK setup time CLK to SYNC hold time CLK to DIN hold time DIN to CLK setup time SYNC to DOUT delay time CLK to DOUT delay time CLK to DOUT disable time DOUT fall time Symbol tR tF fC tWCH tWCL fS tWSH tSX tXS tRD tDR tZD tCO tDZ tDF BIT 1 BIT 2 to 8 "H" -- Conditions VSx0.3VSx0.7 -law , A-law Linear VIH = VSx0.7 VIL =VSx0.3 -- -- -- -- -- -- Value Min. -- -- 64 256 1/fCx0.3 1/fCx0.3 -- 1/fC 100 50 50 50 -- -- -- 10 Typ. -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- Max. 50 50 3152 3152 1/fCx0.7 1/fCx0.3 -- 62 -- -- -- -- 200 200 200 100 Unit ns ns kHz kHz ns ns kHz s ns ns ns ns ns ns ns ns
(2) Microcomputer Data-Related Signals Parameter SRC to SRD data setup time SRC to SRD data hold time SRC to STB setup time SRC pulse width (H) SRC pulse width (L) STB pulse width STB to SRC hold time LO0 to 3 delay time Shift clock frequency Reset pulse width Symbol tSSC tHSC tSCB tWH tWL tDS tHCB tLD fSCLK tWRE Pin SRD, SRC SRC, STB SRC STB STB, SRC LO0 to 3 SRC XPRST Value Min. 50 50 50 200 200 50 50 -- -- 1 Typ. -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 200 2048 -- Unit ns ns ns ns ns ns ns ns kHz s
28
MB86435
3. Transmission Characteristics (1) Microphone Amp System Parameter Gain (between MIC0 and BBO) Gain (between JMIC0 and BBO) Signal to noise ratio (between MIC and BBO) (between XMIC and BBO) Signal to noise ratio (between JMIC and BBO) (between XJMIC and BBO) Symbol Conditions MICO = -20 dBv, 1020 Hz SW3 = on, SW4 = SW5 = SW14 = off EV0 = 0 dB JMICO = -20 dBv, 1020 Hz SW4 = on, SW3 = SW5 = SW14 = off EV0 = 0 dB Ain1 = -40 dBv ( +20 dBgain) SW3 = on, SW4 = SW5 = SW14 = off EV0 = 0 dB, 1020 Hz C message Ain2 = -40 dBv ( +20 dBgain) SW4 = on, SW3 = SW5 = SW14 = off EV0 = 0 dB, 1020 Hz C message Value Min. -1.5 Typ. -- Max. 1.5 Unit
GMB
dB
GJB
-1.5
--
1.5
dB
SMB
40
--
--
dB
SJB
40
--
--
dB
Note: Measurement conditions: s Standard Test Circuit (2) Speaker Amp System Parameter Gain (between EAR and XEAR) Gain (between BBI and JEAR) Gain (between BBI and RAUD) Symbol GBE GBJ GBJ6 GBR WE Output power WT WJ Conditions BBI = -20 dBv, 1020 Hz BBI = -20 dBv, 1020 Hz, ATT = -2.5 dB BBI = -20 dBv, 1020 Hz, ATT = - 8.5 dB BBI = -20 dBv, 1020 Hz SW8 = on, SW6 = SW7 = SW12 = off R = 32 , between EAR-XEAR THD = 10% R = 25 , between TONE-XTONE gain = 0 dB, THD = 10% R = 32 , JEAR, ATT = -2.5 dB THD = 10% Value Min. -- -- -- -- 6.4 10.0 2.0 Typ. -4.3 -2.5 -8.5 0.0 -- -- -- Max. -- -- -- -- -- -- -- Unit dB dB dB dB mW mW mW
Note: Measurement conditions: s Standard Test Circuit (3) TONE System Parameter Symbol GT1 GT2 Conditions 1 tone generated, SW2 = on f1 = 948.1 kHz 2 tone generated, SW2 = on f1 = 948.1 kHz, f2 = 1219.1 kHz Value Min. -- -- Typ. -14.0 -14.0 Max. -- -- Unit dBv dBv
TONE output level (TONE0)
Note: Measurement conditions: s Standard Test Circuit 29
MB86435
(4) Electric Volume System Parameter Volume gain error EV0 (between TAUD-BBO) Volume gain error EV1 (between DIN-PTBO) Volume gain error EV2 (between IM 2-BTO) Volume gain error EV3 (TONEO) Symbol Conditions SW5 = on, SW3 = SW4 = SW14 = off TAUD = -20 dBv, 1020 Hz DIN = -20 dBm0, 1020 Hz Value Min. -0.7 Typ. -- Max. 0.7 Unit
GE0
dB
GE1
-0.8
--
0.8
dB
SE2
IM2 = -20 dBv, 1020 Hz SW2 = on 1 tone generated f1 = 948.1 kHz
-1.0
--
1.0
dB
SE3
-0.5
--
0.5
dB
Note: Measurement conditions: s Standard test circuit (5) Sending/Receiving System (Codec, Analog Block) Parameter Crosstalk (send receive) Crosstalk (send receive) Power supply noise reduction ratio Symbol Conditions Ain1 = 1020 Hz, - 40 dBv (20 dBgain) DIN = ICN Measured at RAUD pin DIN = 1020 Hz, 0 dBm0 AIN = SGC Measured at DOUT pin 0 < f < 50 kHz, VDD + 30 mVOP C message AIN = SGC, DIN = ICN Value Min. -- Typ. -- Max. -50 Unit
CTX
dB
CTR
--
--
-50
dB
PSRR
--
22
--
dB
Note: Measurement conditions: s Standard test circuit
30
MB86435
(6) Codec Parameter Gain tracking (A to D) BTPO DOUT Gain tracking (D to A) DIN PTBO Gain tracking (A to D) (Linear) BTPO DOUT Gain tracking (D to A) (Linear) DIN PTBO Symbol Conditions +3 to -40 dBm0 GTX 1020 Hz, -10 dBm0 Reference value 1020 Hz, -10 dBm0 Reference value EV1 = 0 dB 1020 Hz, AFST-3 dB Reference value 1020 Hz, AFST-3 dB Reference value EV1 = 0 dB -40 to -50 dBm0 -50 to -55 dBm0 +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 AFST to AFST-43 dB GTXL
AFST-43 to AFST-53 dB AFST-53 to AFST-53 dB AFSR to AFSR-43 dB AFSR-43 to AFSR-53 dB AFSR-53 to AFSR-53 dB
Value Min. -0.2 -0.4 -0.8 -0.4 -0.6 -1.0 -0.2 -0.4 -0.8 -0.4 -0.6 -1.0 24.0 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0.02 0.001 0 0.04 0.002 0.7647 Max. 0.2 0.4 0.8 0.4 0.6 1.0 0.2 0.4 0.8 0.4 0.6 1.0 -- -- 0.20 0.8 -- -- -- 0.30 1.10 -- -- -1.0 -- -- 1.20 -- -- --
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB/C dB dB dB/C VOP
GTR
GTRL
0 to 60 Hz Sending frequency characteristics (A to D) BTPO DOUT 0 dBm0 (Linear : AFST-3 dB) 1020 Hz Reference value
60 to 300 Hz -0.20 300 to 3000 Hz -0.20 3000 to 3400 Hz -0.20 3400 to 4600 Hz 4600 to 12 kHz * 32.0
FRX
0 to 300 Hz -0.30 Receiving frequency characteristics (D to A) DIN PTBO FRR 0 dBm0 (Linear : AFSR-3 dB) 1020 Hz Reference value EV1 = 0 dB 300 to 3000 Hz -0.30 3000 to 3400 Hz -0.30 3400 to 4600 Hz 4600 to 12 kHz Sending absolute gain (A to D) BTPO DOUT Receiving absolute gain (D to A) DIN PTBO Absolute level 1020 Hz, 0 dBm0 (Linear : AFST-3 dB) EV1 = 0 dB, VS = 3.0 V, Ta = +25C GAX Power supply variation Temperature variation 1020 Hz, 0 dBm0 (Linear : AFSR-3 dB) VS = 3.0 V, Ta = +25C GAR Power supply variation Temperature variation VABS Over load level -Law = 3.17 dB A-Law = 3.14 dB * 32.0 -1.0 -- -- -1.20 -- -- --
(Continued)
31
MB86435
(Continued)
Parameter Sending signal to noise ratio BTPO DOUT Receiving signal to noise ratio DIN DOUT Sending signal to noise ratio BTPO DOUT (Linear) Recieving signal to noise ratio BTPO DOUT (Linear) Symbol 1020 Hz C message (A to D) 1020 Hz C message (D to A) 1020 Hz C message (A to D) 1020 Hz C message (D to A) C message (A to D) C message (D to A) 1020 Hz, 0 dBm0, Ta = +25C VS = 3.0 V -law 1020 Hz, 0 dBm0, Ta = +25C VS = 3.0 V -law 1020 Hz, 0 dBm0, Ta = +25C A-law VS = 3.0 V 1020 Hz, 0 dBm0, Ta = +25C A-law VS = 3.0 V VS = 3.0 V, Ta = +25C Linear VS = 3.0 V, Ta = +25C Linear FC 1544 kHz (DOUT-DIN short) BTPO = SCG 0-4 kHz (DOUT-DIN short) 4.6-200 kHz BTPO = 0 dBmO, 4.6-200 kHz (DOUT-DIN short) Second and third harmonic,BTPO = 0 dBmO 700-1100 Hz (DOUT-DIN short) } Conditions 0 to -30 dBm0 -40 dBm0 -45 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0
AFST-3 to AFST-33 dB
Value Min. 34.0 28.0 23.0 34.0 28.0 23.0 34.0 28.0 23.0 34.0 28.0 23.0 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -72 -72 Max. -- -- -- -- -- -- -- -- -- -- -- -- -68 -68
Unit dB dB dB dB dB dB dB dB dB dB dB dB
dBm0C
SDX
SDR
SDXL
AFST-43 dB AFST-45 dB
AFSR-3 to AFSR-33 dB
SDRL
AFSR-43 dB AFSR-45 dB
Sending no-talk noise ICNX BTPO DOUT Receiving no-talk noise DIN PTBO Analog input level BTPO Analog output level PTBO Analog input level BTPO Analog output level PTBO ICNR AILU AOLU AILA AOLA
dBm0C
0.3290 0.3739 0.4195 Vrms 0.3290 0.3739 0.4195 Vrms 0.3315 0.3767 0.4227 Vrms 0.3315 0.3767 0.4227 Vrms 0.6729 0.7647 0.8581 VOP
Analog input fullscale level AFST BTPO Analog output fullscale level PTBO AFSR
0.6729 0.7647 0.8581 -- -- 30 43 490 -- -- -- 550 -70 -50 -- --
VOP s dBm0 dBm0 dB dB
Overall absolute delay PDA (BTPO PTBO) Single frequency noise (BTPO PTBO) Discrimination (BTPO PTBO) In-band spurious response (BTPO PTBO) *: 14.5 x {1 - SIN SFNA DISA IBSA (4000 - f) 1200
32
MB86435
s STANDARD TEST CIRCUIT
100 k 100 k 0.1F 0.1F VRH 0.1F SGC 0.1F SGO Dout 8 kHz 2 MHz Din DOUT SYNC CLK EV1 DIN PTBO 100 k TAUD 100 k 0.1F 100 k 100 k 100 k 0.039F BTO 100 k IM3 100 k BBI 0.1F TONEO 22F TCLK TONE TONC IMTON TONE DATA LATCH P SAVE 0.1F SRD SRC STB XPRST LO0 LO1 LO2 LO3 PSC0 PSC1 PSC2 LED XTONE 25 100 k 100 k EV3 JEAR 32 XEAR 32 EAR AMP3 RAUD IM1 OP1 IM2 OP2 DSDT AMP1 EXSD AMP2 EV2 DSCK CODEC JMICO 100 k + JMIC 10 k XJMIC SGC Ain2 EV0 + MIC 10 k XMIC SGC BTPO BTPI BBO MICO 100 k Ain1
: Digital input
: Digital output
: Analog input
: Analog output
: Input/output
: V DD
: GND
Note: Sufficient path capacitance must be placed between VDDAB-BAG, VDDAC-CAG, VDDSP1-SPG1, VDDSP2-SPG2, VDD-AG.
33
MB86435
s ORDERING INFORMATION
Part number MB86435PFV Package 64 pins, Plastic LQFP (FPT-64P-M03) Remarks
34
MB86435
s PACKAGE DIMENSION
64 pin Plastic LQFP (FPT-64P-M03)
12.000.20(.472.008)SQ
48
10.000.10(.394.004)SQ
1.50 -0.10 (MOUNTING HEIGHT) +.008 .059 -.004
33
+0.20
49
32
7.50 (.295) REF INDEX
11.00 (.433) NOM
64
17 1 16
+0.08
Details of "A" part "A" 0.127 -0.02 +.002 .005 -.001
+0.05
LEAD No.
0.500.08 (.0197.0031)
0.18 -0.03 +.003 .007 -.001
0.100.10 (STAND OFF) (.004.004)
0.500.20 (.020.008) 0.10(.004) 0 10
C
1995 FUJITSU LIMITED F64009S-2C-5
Dimensions in mm (inches)
35
MB86435
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9703 (c) FUJITSU LIMITED Printed in Japan
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